The unreachable instruction causes an unconditional trap.
A trap immediately aborts execution. Traps cannot be handled by WebAssembly code, but are reported to the outside environment, where they typically can be caught.
The instructions after it are still validated, but against an unconstrained operand stack, so sequences that would not otherwise type-check are accepted there.
Stack
[t1*] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Blocks, unreachable, WebAssembly 1.0.
0x01nop
do nothing
Description
The nop instruction does nothing.
Stack
[] → []
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Blocks, nop, WebAssembly 1.0.
0x02block bt
Description
The beginning of a block construct, a sequence of instructions with a label at the end.
Both the parameter and result types come from the bt immediate.
The block, loop and if instructions are structured instructions. They bracket nested sequences of instructions, called blocks, terminated with, or separated by, end or else pseudo-instructions. They must be well-nested.
Stack
[t1*] → [t2*]
Immediate operands
s33 bt : blocktype — 0x40 for no result; one valtype byte (0x7F i32, 0x7E i64, 0x7D f32, 0x7C f64, 0x7B v128, or a reference type) for one result; or a typeidx of 0 or more, naming a function type, for a block that takes or returns more than one value
Then the block’s instructions, then 0x0B (end).
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Blocks, block, takes immediates, WebAssembly 1.0.
0x03loop bt
Description
A block with a label at the beginning which may be used to form loops.
Stack
[t1*] → [t2*]
Both the parameter and result types come from the bt immediate.
Immediate operands
s33 bt : blocktype — 0x40 for no result; one valtype byte (0x7F i32, 0x7E i64, 0x7D f32, 0x7C f64, 0x7B v128, or a reference type) for one result; or a typeidx of 0 or more, naming a function type, for a block that takes or returns more than one value
Then the block’s instructions, then 0x0B (end).
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Blocks, loop, takes immediates, WebAssembly 1.0.
0x04if bt
Description
The beginning of an if construct with an implicit then block.
Stack
[t1* i32] → [t2*]
Both the parameter and result types come from the bt immediate.
The i32 on top is the condition: non-zero runs the first branch, zero runs the else-branch if there is one.
Immediate operands
s33 bt : blocktype — 0x40 for no result; one valtype byte (0x7F i32, 0x7E i64, 0x7D f32, 0x7C f64, 0x7B v128, or a reference type) for one result; or a typeidx of 0 or more, naming a function type, for a block that takes or returns more than one value
Then the instructions run when the condition is non-zero. Optionally 0x05 (else) and the instructions run when it is zero. Then 0x0B (end).
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Blocks, if, takes immediates, WebAssembly 1.0.
0x05else
Description
Marks the else block of an if.
Not typed on its own: what it does to the stack belongs to the enclosing if.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Blocks, else, WebAssembly 1.0.
0x06try bt
Description
Begins a block which can handle thrown exceptions.
Stack
[t1*] → [t2*]
Both the parameter and result types come from the bt immediate.
Immediate operands
s33 bt : blocktype — 0x40 for no result; one valtype byte (0x7F i32, 0x7E i64, 0x7D f32, 0x7C f64, 0x7B v128, or a reference type) for one result; or a typeidx of 0 or more, naming a function type, for a block that takes or returns more than one value
Then the instructions. Then zero or more 0x07 (catch) clauses, optionally ending with 0x19 (catch_all), or a single 0x18 (delegate). Then 0x0B (end).
⚠️Legacy (2023)Replaced by try_table (0x1F) and throw_ref (0x0A)
The exception handling design that preceded try_table. Engines still accept it and older toolchains still emit it, but new code should use the standardised form.Engine support
Properties
Control flow, Exceptions, try, takes immediates, legacy, Legacy exception handling.
0x07catch x
Description
Begins the catch block of the try block.
Not typed on its own: what it does to the stack belongs to the enclosing try.
⚠️Legacy (2023)Replaced by try_table (0x1F) and throw_ref (0x0A)
The exception handling design that preceded try_table. Engines still accept it and older toolchains still emit it, but new code should use the standardised form.Engine support
Properties
Control flow, Exceptions, catch, takes immediates, legacy, Legacy exception handling.
0x08throw x
Description
Creates an exception defined by the tag and then throws it.
Stack
[t1*t*] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
t* are the parameters of tag x.
Immediate operands
u32 x : tagidx
Status
Exception handlingStandardised in WebAssembly 3.0 (2025)Standardised. This is the try_table form; the earlier try/catch encoding is still emitted by older toolchains.Engine support
Properties
Control flow, Exceptions, throw, takes immediates, Exception handling.
0x09rethrow l
Description
Pops the exnref on top of the stack and throws it.
Stack
[t1* i32] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
⚠️Legacy (2023)Replaced by try_table (0x1F) and throw_ref (0x0A)
The exception handling design that preceded try_table. Engines still accept it and older toolchains still emit it, but new code should use the standardised form.Engine support
Properties
Control flow, Exceptions, rethrow, takes immediates, legacy, Legacy exception handling.
0x0Athrow_ref
Description
Pops the exnref on top of the stack and throws it.
Stack
[t1* exnref] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
Traps on a null exception reference.
Status
Exception handlingStandardised in WebAssembly 3.0 (2025)Standardised. This is the try_table form; the earlier try/catch encoding is still emitted by older toolchains.Engine support
Properties
Control flow, Exceptions, throw_ref, Exception handling.
0x0Bend
Description
Marks the end of a block, loop, if, or function.
Not typed on its own: what it does to the stack belongs to the construct it closes.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Blocks, end, WebAssembly 1.0.
0x0Cbr l
branch to a label
Description
Branch to a given label in an enclosing construct.
Performs an unconditional branch.
A branch targeting a block or if behaves like a break statement in most C-like languages, while a branch targeting a loop behaves like a continue statement.
Stack
[t1*t*] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
Immediate operands
u32 l : labelidx
Label 0 is the innermost structured instruction enclosing the branch; increasing indices refer to those further out.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Branches, br, takes immediates, WebAssembly 1.0.
0x0Dbr_if l
Description
Performs a conditional branch, branching if i32 c is non-zero.
Conditionally branch to a given label in an enclosing construct.
Stack
[t* i32] → [t*]
Immediate operands
u32 l : labelidx
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Branches, br_if, takes immediates, WebAssembly 1.0.
0x0Ebr_table l* l
Description
A jump table which jumps to a label in an enclosing construct.
Performs an indirect branch through an operand indexing into the label vector that is an immediate to the instruction, or to a default target if the operand is out of bounds.
Stack
[t1*t* i32] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
Immediate operands
u32 l* : list(labelidx) — the branch table
u32 l : labelidx — the default target
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Branches, br_table, takes immediates, WebAssembly 1.0.
0x0Freturn
return from the function
Description
Return zero or more values from this function.
The return instruction is a shortcut for an unconditional branch to the outermost block, which implicitly is the body of the current function.
Stack
[t1*t*] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Calls, return, WebAssembly 1.0.
0x10call x
call a function
Description
The call instruction invokes another function, consuming the necessary arguments from the stack and returning the result values of the call.
Stack
[t1*] → [t2*]
Immediate operands
u32 x : funcidx
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Calls, call, takes immediates, WebAssembly 1.0.
0x11call_indirect y x
Description
The call_indirect instruction calls a function indirectly through an operand indexing into a table.
Stack
[t1* i32] → [t2*]
The i32 selects an entry of table x; the call traps unless that entry holds a function of type y. Before reference types this second immediate was always 0x00, the only table there was.
Immediate operands
u32 y : typeidx
u32 x : tableidx
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Control flow, Calls, call_indirect, takes immediates, WebAssembly 1.0.
0x12return_call x
Description
The tail-call version of call.
The current frame is replaced instead of a new one being pushed, so a chain of tail calls runs in constant stack space.
Stack
[t1*t*] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
t* are the parameters of function x. The callee’s results become the current function’s, so execution does not continue past this instruction.
Immediate operands
u32 x : funcidx
Status
Tail callStandardised in WebAssembly 3.0 (2025)Standardised. Shipping in current browsers; check support if you target older engines.Engine support
Properties
Control flow, Calls, return_call, takes immediates, Tail call.
0x13return_call_indirect y x
Description
The tail-call version of call_indirect.
The current frame is replaced instead of a new one being pushed, so a chain of tail calls runs in constant stack space.
Stack
[t1*t* i32] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
t* are the parameters of function type y, and the i32 indexes table x. The callee’s results become the current function’s, so execution does not continue past this instruction.
Immediate operands
u32 y : typeidx
u32 x : tableidx
Status
Tail callStandardised in WebAssembly 3.0 (2025)Standardised. Shipping in current browsers; check support if you target older engines.Engine support
Properties
Control flow, Calls, return_call_indirect, takes immediates, Tail call.
0x14call_ref x
Description
Calls a function through a reference of type x.
Stack
[t1* (ref null x)] → [t2*]
t1* and t2* are the parameters and results of function type x. Traps on a null reference.
Immediate operands
u32 x : typeidx
Status
Typed function referencesStandardised in WebAssembly 3.0 (2025)Standardised. Shipping in current browsers; check support if you target older engines.Engine support
Properties
Control flow, Calls, call_ref, takes immediates, Typed function references.
0x15return_call_ref x
Description
The tail-call version of call_ref.
The current frame is replaced instead of a new one being pushed, so a chain of tail calls runs in constant stack space.
Stack
[t1*t* (ref null x)] → [t2*]
Stack-polymorphic: execution jumps away and never continues past this instruction, so the validator accepts whatever is left on the stack.
t* are the parameters of function type x. The callee’s results become the current function’s, so execution does not continue past this instruction. Traps on a null reference.
Immediate operands
u32 x : typeidx
Status
Typed function referencesStandardised in WebAssembly 3.0 (2025)Standardised. Shipping in current browsers; check support if you target older engines.Engine support
Properties
Control flow, Calls, return_call_ref, takes immediates, Typed function references.
0x18delegate l
Description
Begins the delegate block of the try block.
Not typed on its own: what it does to the stack belongs to the enclosing try.
⚠️Legacy (2023)Replaced by try_table (0x1F) and throw_ref (0x0A)
The exception handling design that preceded try_table. Engines still accept it and older toolchains still emit it, but new code should use the standardised form.Engine support
Properties
Control flow, Exceptions, delegate, takes immediates, legacy, Legacy exception handling.
0x19catch_all
Description
Begins the catch_all block of the try block.
Not typed on its own: what it does to the stack belongs to the enclosing try.
⚠️Legacy (2023)Replaced by try_table (0x1F) and throw_ref (0x0A)
The exception handling design that preceded try_table. Engines still accept it and older toolchains still emit it, but new code should use the standardised form.Engine support
Properties
Control flow, Exceptions, catch_all, legacy, Legacy exception handling.
0x1Adrop
discard the top of the stack
Description
The drop instruction simply throws away a single operand.
Arguably the only stack manipulation instruction WebAssembly has. There is no dup, swap or rot, and no way to reach past the top of the stack. See WebAssembly is not quite a stack machine, by purplesyringa.
Stack
[t] → []
Works on any single value: t is whatever is on top.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
The select instruction selects one of its first two operands based on whether its third operand is zero or not.
Stack
[tt i32] → [t]
Works on any value type, as long as both candidates have the same one, but only a number or vector type. For a reference, use the annotated form select t (0x1C).
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Properties
Parametric, select, WebAssembly 1.0.
0x1Cselect t t*
Description
Only the annotated form can be used with reference types.
Stack
[tt i32] → [t]
Value-polymorphic: works on any value type — t is whatever the operands are.
t is given by the immediate rather than inferred, which is what lets this form take a reference.
Immediate operands
t* : list(valtype) — currently exactly one
Status
Reference typesStandardised in WebAssembly 2.0 (2022)Standardised and supported by every current engine.Engine support
Begins a block which can handle thrown exceptions.
Stack
[t1*] → [t2*]
Both the parameter and result types come from the bt immediate.
Immediate operands
s33 bt : blocktype — 0x40 for no result; one valtype byte (0x7F i32, 0x7E i64, 0x7D f32, 0x7C f64, 0x7B v128, or a reference type) for one result; or a typeidx of 0 or more, naming a function type, for a block that takes or returns more than one value
c* : list(catch) — 0x00xl (catch), 0x01xl (catch_ref), 0x02l (catch_all) or 0x03l (catch_all_ref), where x is a tagidx and l a labelidx
Then the instructions, then 0x0B (end).
Status
Exception handlingStandardised in WebAssembly 3.0 (2025)Standardised. This is the try_table form; the earlier try/catch encoding is still emitted by older toolchains.Engine support
Properties
Control flow, Exceptions, try_table, takes immediates, Exception handling.
0x20local.get x
Description
This instruction gets the value of a variable.
The index space for locals is only accessible inside a function and includes the parameters of that function, which precede the local variables.
The locals context refers to the list of locals declared in the current function (including parameters), represented by their value type.
Stack
[] → [t]
Immediate operands
u32 x : localidx
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
The signatures on the memory instructions show a 32-bit memory. A 64-bit memory (memory64) takes and returns i64 addresses instead, including for memory.size and memory.grow.
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
The static offset is added to the address operand taken from the stack. For a 32-bit memory the sum is computed in 33 bits, so it cannot wrap; a 64-bit memory (memory64) takes an i64 address instead. All values are read and written in little endian byte order. A trap results if any accessed byte lies outside the memory’s current size.
Stack
[i32] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Note: When a number is stored into memory, it is converted into a sequence of bytes in little endian byte order.
Stack
[i32] → [f32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
Integer loads and stores can optionally specify a storage size that is smaller than the bit width of the respective value type. In the case of loads, a sign extension mode sx (s|u) is then required to select appropriate behavior.
Stack
[i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
The memory.size instruction returns the current size of a memory.
Operates in units of page size. Each page is 65,536 bytes (64KB).
Stack
[] → [i32]
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
The memory.grow instruction grows memory by a given delta and returns the previous size, or −1 if enough memory cannot be allocated.
Operates in units of page size. Each page is 65,536 bytes (64KB).
Stack
[i32] → [i32]
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Status
WebAssembly 1.0Standardised in WebAssembly 1.0 (2017)Part of the original WebAssembly release. Supported everywhere WebAssembly is.
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
Status
Reference typesStandardised in WebAssembly 2.0 (2022)Standardised and supported by every current engine.Engine support
1 if the two are the same reference or both null, 0 otherwise.
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Converts a nullable reference to a non-nullable one or traps if null.
Stack
[(ref null ht)] → [(ref ht)]
Traps on null.
Status
Typed function referencesStandardised in WebAssembly 3.0 (2025)Standardised. Shipping in current browsers; check support if you target older engines.Engine support
Properties
Reference, as, Typed function references.
0xD5br_on_null l
Description
Converts a nullable reference to a non-nullable one or branches if null.
Stack
[t* (ref null ht)] → [t* (ref ht)]
Branches to l if the reference is null; otherwise leaves it on the stack, now known to be non-null.
Immediate operands
u32 l : labelidx
Status
Typed function referencesStandardised in WebAssembly 3.0 (2025)Standardised. Shipping in current browsers; check support if you target older engines.Engine support
Properties
Control flow, Branches, br_on_null, takes immediates, Typed function references.
0xD6br_on_non_null l
Description
Checks for null and branches if present.
Stack
[t* (ref null ht)] → [t*]
Branches to l if the reference is not null, carrying it to the label; otherwise leaves nothing.
Immediate operands
u32 l : labelidx
Status
Typed function referencesStandardised in WebAssembly 3.0 (2025)Standardised. Shipping in current browsers; check support if you target older engines.Engine support
Properties
Control flow, Branches, br_on_non_null, takes immediates, Typed function references.
0xE0cont.new x
Description
Part of the stack switching proposal, which adds continuations so a module can run several execution stacks — coroutines, generators, async/await and lightweight threads.
Stack
[(ref null ft)] → [(ref x)]
ft is the function type that continuation type x wraps. Turns a function into a continuation that has not started running.
Adds continuations for coroutines, generators and async. Encoding not final.Engine support
Properties
Control flow, Stack switching, new, takes immediates, proposal, Stack switching.
0xE1cont.bind x y
Description
Part of the stack switching proposal, which adds continuations so a module can run several execution stacks — coroutines, generators, async/await and lightweight threads.
Stack
[t* (ref null x)] → [(ref y)]
Types: t* are arguments bound into the continuation ahead of time, which is why y takes fewer parameters than x. The specification writes them t3*.
Adds continuations for coroutines, generators and async. Encoding not final.Engine support
Properties
Control flow, Stack switching, bind, takes immediates, proposal, Stack switching.
0xE2suspend x
Description
Part of the stack switching proposal, which adds continuations so a module can run several execution stacks — coroutines, generators, async/await and lightweight threads.
Stack
[t1*] → [t2*]
t1* and t2* are the parameters and results of tag x. Suspends to the nearest handler for that tag.
Adds continuations for coroutines, generators and async. Encoding not final.Engine support
Properties
Control flow, Stack switching, suspend, takes immediates, proposal, Stack switching.
0xE3resume x h*
Description
Part of the stack switching proposal, which adds continuations so a module can run several execution stacks — coroutines, generators, async/await and lightweight threads.
Stack
[t1* (ref null x)] → [t2*]
t1* and t2* are the parameters and results of continuation type x. The handler clauses say where control goes if the continuation suspends.
Adds continuations for coroutines, generators and async. Encoding not final.Engine support
Properties
Control flow, Stack switching, resume, takes immediates, proposal, Stack switching.
0xE4resume_throw x e h*
Description
Part of the stack switching proposal, which adds continuations so a module can run several execution stacks — coroutines, generators, async/await and lightweight threads.
Stack
[t* (ref null x)] → [t2*]
Types: t* are the parameters of tag e, raised at the point where the continuation suspended. t2* are the results of continuation type x.
Adds continuations for coroutines, generators and async. Encoding not final.Engine support
Properties
Control flow, Stack switching, resume_throw, takes immediates, proposal, Stack switching.
0xE5resume_throw_ref x h*
Description
Part of the stack switching proposal, which adds continuations so a module can run several execution stacks — coroutines, generators, async/await and lightweight threads.
Stack
[exnref (ref null x)] → [t2*]
Takes an existing exception reference rather than a tag’s parameters, as throw_ref does beside throw. t2* are the results of continuation type x.
Adds continuations for coroutines, generators and async. Encoding not final.Engine support
Properties
Control flow, Stack switching, resume_throw_ref, takes immediates, proposal, Stack switching.
0xE6switch x y
Description
Part of the stack switching proposal, which adds continuations so a module can run several execution stacks — coroutines, generators, async/await and lightweight threads.
Stack
[t1* (ref null x)] → [t2*]
t1* and t2* are the parameters and results of continuation type x. Switches straight to another continuation rather than suspending to a handler.
Adds continuations for coroutines, generators and async. Encoding not final.Engine support
Properties
Control flow, Stack switching, switch, takes immediates, proposal, Stack switching.
0xFBopcode prefix
The first byte (prefix) of a multi-byte opcode. While the prefix is always a single byte, the sub-opcode which follows is variable-length: an unsigned 32-bit integer stored with Little Endian Base 128 (LEB128) encoding. For multi-byte opcodes, the prefix and sub-opcode together form an opcode. An opcode is 2-bytes when the sub-opcode has a value 0 to 127, and 3-bytes when it reaches 128, at which point variable encoding begins to differ from typical integer representations. The theoretical maximum for a 2-byte sub-opcode (in a 3-byte opcode) is 16,383. The instructions (opcodes) prefixed with 0xFB are listed in Table B.
The first byte (prefix) of a multi-byte opcode. While the prefix is always a single byte, the sub-opcode which follows is variable-length: an unsigned 32-bit integer stored with Little Endian Base 128 (LEB128) encoding. For multi-byte opcodes, the prefix and sub-opcode together form an opcode. An opcode is 2-bytes when the sub-opcode has a value 0 to 127, and 3-bytes when it reaches 128, at which point variable encoding begins to differ from typical integer representations. The theoretical maximum for a 2-byte sub-opcode (in a 3-byte opcode) is 16,383. The instructions (opcodes) prefixed with 0xFC are listed in Table C.
The first byte (prefix) of a multi-byte opcode. While the prefix is always a single byte, the sub-opcode which follows is variable-length: an unsigned 32-bit integer stored with Little Endian Base 128 (LEB128) encoding. For multi-byte opcodes, the prefix and sub-opcode together form an opcode. An opcode is 2-bytes when the sub-opcode has a value 0 to 127, and 3-bytes when it reaches 128, at which point variable encoding begins to differ from typical integer representations. The theoretical maximum for a 2-byte sub-opcode (in a 3-byte opcode) is 16,383. The instructions (opcodes) prefixed with 0xFD are listed in Table D SIMD.
The first byte (prefix) of a multi-byte opcode. While the prefix is always a single byte, the sub-opcode which follows is variable-length: an unsigned 32-bit integer stored with Little Endian Base 128 (LEB128) encoding. For multi-byte opcodes, the prefix and sub-opcode together form an opcode. An opcode is 2-bytes when the sub-opcode has a value 0 to 127, and 3-bytes when it reaches 128, at which point variable encoding begins to differ from typical integer representations. The theoretical maximum for a 2-byte sub-opcode (in a 3-byte opcode) is 16,383. The instructions (opcodes) prefixed with 0xFE are listed in Table E Threads & Atomics.
Allocates a struct of type x, taking one value per field from the stack.
Stack
[t*] → [(ref x)]
One value per field of type x, in declaration order. A packed i8 or i16 field takes an i32.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Allocates a struct of type x with every field at its default value.
Stack
[] → [(ref x)]
Every field gets the default value for its type.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
t is the type of field y. Only for an unpacked field. A packed i8 or i16 field is read with get_s or get_u, which extend it into an i32. Traps on a null reference.
Immediate operands
u32 x : typeidx
u32 y : fieldidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Reads packed field y of struct type x, sign-extending it into an i32.
Stack
[(ref null x)] → [i32]
Packed field: it is an i8 or an i16, so it is read into an i32: sign-extended by struct.get_s, zero-extended by struct.get_u.
Immediate operands
u32 x : typeidx
u32 y : fieldidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Reads packed field y of struct type x, zero-extending it into an i32.
Stack
[(ref null x)] → [i32]
Packed field: it is an i8 or an i16, so it is read into an i32: sign-extended by struct.get_s, zero-extended by struct.get_u.
Immediate operands
u32 x : typeidx
u32 y : fieldidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
t is the type of field y, which must be mutable. Traps on a null reference.
Immediate operands
u32 x : typeidx
u32 y : fieldidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Allocates an array of type x, every element set to the same value.
Stack
[t i32] → [(ref x)]
t is the element type of x: the value to fill with, then how many elements.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Allocates an array of type x with every element at its default value.
Stack
[i32] → [(ref x)]
How many elements; each gets the default value for the element type.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Allocates an array of type x with a fixed number of elements, taken from the stack.
Stack
[t*] → [(ref x)]
One value per element. How many there are is the immediate n, not an operand.
Immediate operands
u32 x : typeidx
u32 n — the number of elements
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Allocates an array of type x, initialised from data segment y.
Stack
[i32 i32] → [(ref x)]
Offset into data segment y, then how many elements to read from it.
Immediate operands
u32 x : typeidx
u32 y : dataidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Allocates an array of type x, initialised from element segment y.
Stack
[i32 i32] → [(ref x)]
Offset into element segment y, then how many elements to read from it.
Immediate operands
u32 x : typeidx
u32 y : elemidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
The array, then the index. t is the element type of x. Only for an unpacked field. A packed i8 or i16 field is read with get_s or get_u, which extend it into an i32. Traps on a null reference.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Reads a packed element of array type x, sign-extending it into an i32.
Stack
[(ref null x) i32] → [i32]
Packed field: it is an i8 or an i16, so it is read into an i32: sign-extended by array.get_s, zero-extended by array.get_u.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Reads a packed element of array type x, zero-extending it into an i32.
Stack
[(ref null x) i32] → [i32]
Packed field: it is an i8 or an i16, so it is read into an i32: sign-extended by array.get_s, zero-extended by array.get_u.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Array, index, then the value. The element type must be mutable. Traps on a null reference.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Array, the offset to start at, the value to write, then how many elements. Traps on a null reference, or on the range running past the end.
Immediate operands
u32 x : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Copies a range of elements from one array to another. Both may be the same array.
Stack
[(ref null x) i32 (ref null y) i32 i32] → []
Destination array and offset, source array and offset, then how many elements. Traps on either being null, or on either range running past the end.
Immediate operands
u32 x : typeidx
u32 y : typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Copies bytes from data segment y into a range of an array.
The array’s elements have to be numeric or packed, since a data segment is raw bytes.
Stack
[(ref null x) i32 i32 i32] → []
Array, the offset to start at, the offset into data segment y, then how many elements.
Immediate operands
u32 x : typeidx
u32 y : dataidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Copies references from element segment y into a range of an array.
Stack
[(ref null x) i32 i32 i32] → []
Array, the offset to start at, the offset into element segment y, then how many elements.
Immediate operands
u32 x : typeidx
u32 y : elemidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Types: ht′ is any supertype of ht, so the operand may be any reference in the same type hierarchy. Pushes 1 if the reference matches, 0 if not, and 0 for null.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Types: ht′ is any supertype of ht, so the operand may be any reference in the same type hierarchy. Pushes 1 if the reference matches, 0 if not. Null counts as a match.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Types: ht′ is any supertype of ht, so the operand may be any reference in the same type hierarchy. Traps if the reference does not match, and on null.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Types: ht′ is any supertype of ht, so the operand may be any reference in the same type hierarchy. Traps if the reference does not match. Null passes.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
rt1 and rt2 are the two immediate heap types, each made nullable or not by a bit of the castflags byte. Branches to l with the reference typed rt2 if it matches; otherwise leaves it on the stack with rt2 subtracted from its type, which is what the backslash means.
Immediate operands
u8 f : castflags — which of the two heap types is nullable
u32 l : labelidx
s33 ht1 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the source type
s33 ht2 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the type being tested for
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Branches if a reference does not have a given heap type.
Stack
[t*rt1] → [t*rt2]
rt1 and rt2 are the two immediate heap types, each made nullable or not by a bit of the castflags byte. The mirror of br_on_cast: branches when the reference does not match.
Immediate operands
u8 f : castflags — which of the two heap types is nullable
u32 l : labelidx
s33 ht1 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the source type
s33 ht2 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the type being tested for
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Converts an external value into the internal representation.
Stack
[externref] → [anyref]
Nullability is carried through: a non-null operand gives a non-null result, and null converts to null.
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Converts an internal value into the external representation.
Stack
[anyref] → [externref]
Nullability is carried through: a non-null operand gives a non-null result, and null converts to null.
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Creates an i31ref from a 32 bit value, truncating high bit.
Stack
[i32] → [(ref i31)]
Only the low 31 bits are kept; the value is not boxed on the heap.
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Sign-extends the 31-bit value to i32. Traps on a null reference.
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Zero-extends the 31-bit value to i32. Traps on a null reference.
Status
Garbage collectionStandardised in WebAssembly 3.0 (2025)Standardised as part of WebAssembly 3.0 and shipping in browsers since late 2023. These encodings replace the 2022 draft, which used *_canon names and a sparser numbering.Engine support
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Allocates a struct with an explicit descriptor, taking the descriptor and the field values.
The 2022 draft of the GC proposal used this byte for i31.new; that draft was replaced before it was standardised, and the byte is being assigned again.
Stack
[t* (ref null (exact y))] → [(ref (exact x))]
The field values, then the descriptor on top. y is the descriptor type declared for x.
Allocates a struct with an explicit descriptor, its fields set to their defaults.
The 2022 draft of the GC proposal used this byte for i31.get_s; that draft was replaced before it was standardised, and the byte is being assigned again.
Stack
[(ref null (exact y))] → [(ref (exact x))]
The descriptor. Every field gets the default value for its type.
Reads the descriptor a reference was allocated with.
The 2022 draft of the GC proposal used this byte for i31.get_u; that draft was replaced before it was standardised, and the byte is being assigned again.
Stack
[(ref null (exact x))] → [(ref (exact y))]
y is the descriptor type declared for x. Traps on a null reference.
Types: x is the type named by the immediate and y its declared descriptor type. The reference to cast comes first, then the descriptor to compare it against; the cast succeeds where the reference’s own descriptor is that same object. Traps on a mismatch, and on null.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
Types: x is the type named by the immediate and y its declared descriptor type. The reference to cast comes first, then the descriptor to compare it against; the cast succeeds where the reference’s own descriptor is that same object. Traps on a mismatch. Null passes.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
Branches if a reference’s descriptor is the one given.
Stack
[t*rt1 (ref null (exact y))] → [t*rt1\rt2]
Types: rt1 and rt2 are the two immediate heap types, each made nullable or not by a bit of the castflags byte. Matches on descriptor identity rather than on the type alone. Branches to l with the reference typed rt2 if it matches; otherwise leaves it with rt2 subtracted from its type, which is what the backslash means.
Immediate operands
u8 f : castflags — which of the two heap types is nullable
u32 l : labelidx
s33 ht1 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the source type
s33 ht2 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the type being tested for
Branches if a reference’s descriptor is not the one given.
Stack
[t*rt1 (ref null (exact y))] → [t*rt2]
Types: rt1 and rt2 are the two immediate heap types, each made nullable or not by a bit of the castflags byte. The mirror of br_on_cast_desc_eq: branches when the reference does not match.
Immediate operands
u8 f : castflags — which of the two heap types is nullable
u32 l : labelidx
s33 ht1 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the source type
s33 ht2 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the type being tested for
An encoding from the 2022 draft of the GC proposal. The final encoding, standardised in 2023, has this as ref.test (0xFB 20).
Stack
[(ref null ht′)] → [i32]
2022 draft: a draft encoding, abandoned before the proposal was finished. The instruction it became is typed the same way.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
An encoding from the 2022 draft of the GC proposal. The final encoding, standardised in 2023, has this as ref.cast (0xFB 22).
Stack
[(ref null ht′)] → [(ref ht)]
2022 draft: a draft encoding, abandoned before the proposal was finished. The instruction it became is typed the same way.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
An encoding from the 2022 draft of the GC proposal. The final encoding, standardised in 2023, has this as br_on_cast (0xFB 24).
Stack
[t*rt1] → [t*rt1]
2022 draft: a draft encoding, abandoned before the proposal was finished. It took only a labelidx and a single heaptype, with no castflags byte.
Immediate operands
u8 f : castflags — which of the two heap types is nullable
u32 l : labelidx
s33 ht1 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the source type
s33 ht2 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the type being tested for
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
An encoding from the 2022 draft of the GC proposal. The final encoding, standardised in 2023, has this as br_on_cast_fail (0xFB 25).
Stack
[t*rt1] → [t*rt2]
2022 draft: a draft encoding, abandoned before the proposal was finished. It took only a labelidx and a single heaptype, with no castflags byte.
Immediate operands
u8 f : castflags — which of the two heap types is nullable
u32 l : labelidx
s33 ht1 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the source type
s33 ht2 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the type being tested for
⛔Withdrawn (2023)Replaced by br_on_cast_fail (0xFB 25)
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
An encoding from the 2022 draft of the GC proposal. The final encoding, standardised in 2023, has this as ref.test null (0xFB 21).
Stack
[(ref null ht′)] → [i32]
2022 draft: a draft encoding, abandoned before the proposal was finished. The instruction it became is typed the same way.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
⛔Withdrawn (2023)Replaced by ref.test null (0xFB 21)
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
An encoding from the 2022 draft of the GC proposal. The final encoding, standardised in 2023, has this as ref.cast null (0xFB 23).
Stack
[(ref null ht′)] → [(ref null ht)]
2022 draft: a draft encoding, abandoned before the proposal was finished. The instruction it became is typed the same way.
Immediate operands
s33 ht : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx
⛔Withdrawn (2023)Replaced by ref.cast null (0xFB 23)
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
An encoding from the 2022 draft of the GC proposal. The final encoding, standardised in 2023, has this as br_on_cast (0xFB 24).
Stack
[t*rt1] → [t*rt1]
2022 draft: a draft encoding, abandoned before the proposal was finished. It took only a labelidx and a single heaptype, with no castflags byte.
Immediate operands
u8 f : castflags — which of the two heap types is nullable
u32 l : labelidx
s33 ht1 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the source type
s33 ht2 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the type being tested for
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
An encoding from the 2022 draft of the GC proposal. The final encoding, standardised in 2023, has this as br_on_cast_fail (0xFB 25).
Stack
[t*rt1] → [t*rt2]
2022 draft: a draft encoding, abandoned before the proposal was finished. It took only a labelidx and a single heaptype, with no castflags byte.
Immediate operands
u8 f : castflags — which of the two heap types is nullable
u32 l : labelidx
s33 ht1 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the source type
s33 ht2 : heaptype — a negative one-byte value is an abstract type (0x70 func, 0x6F extern, 0x6E any, 0x6D eq, 0x6C i31, 0x6B struct, 0x6A array, 0x69 exn, 0x74 noexn, 0x73 nofunc, 0x72 noextern, 0x71 none); a value of 0 or more is a typeidx — the type being tested for
⛔Withdrawn (2023)Replaced by br_on_cast_fail (0xFB 25)
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
⛔Withdrawn (2023)Replaced by any.convert_extern (0xFB 26)
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
⛔Withdrawn (2023)Replaced by extern.convert_any (0xFB 27)
An encoding from the draft of the garbage collection proposal, replaced before it was standardised. These slots are unassigned today; the entries are here because old modules and old tools may still use them.
Reads UTF-8 bytes from memory and returns a new string. Traps if they are not valid UTF-8.
Stack
[i32 i32] → [stringref]
Address in memory x, then how many code units to read.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Reads 16-bit code units from memory and returns a new string.
WTF-16: UTF-16 extended to allow isolated surrogates, which is exactly what a JavaScript string is.
Stack
[i32 i32] → [stringref]
Address in memory x, then how many 16-bit code units to read.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Measures the string in WTF-8, which is also what a lossy UTF-8 encoding would need: an isolated surrogate takes three bytes in WTF-8, and so does the U+FFFD that replaces it.
WTF-8: UTF-8 extended to allow isolated surrogates, the lone halves of surrogate pairs that a JavaScript string can hold and UTF-8 cannot encode.
Writes the string to memory as UTF-8. Traps on an isolated surrogate, which UTF-8 cannot encode.
Nothing bounds the write but the memory itself, so measure first.
Stack
[stringref i32] → [i32]
The string, then the destination address in memory x. Pushes how many code units were written.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Writes the string to memory as 16-bit code units, little-endian.
WTF-16: UTF-16 extended to allow isolated surrogates, which is exactly what a JavaScript string is.
Stack
[stringref i32] → [i32]
The string, then the destination address in memory x. Pushes how many code units were written.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Compares two strings by contents, not by identity.
Stack
[stringref stringref] → [i32]
1 if the two strings have the same contents, 0 if not. Two nulls are equal and one null is not: this is the only string instruction that accepts a null reference, and the rest trap on one.
No engine implements it, and the encoding may still change. Included for reference rather than for use.Engine support
Properties
Strings, is, 3-byte opcode, dormant, Reference-typed strings.
0xFB139:u32string.new_lossy_utf8 x
Description
Reads UTF-8 bytes from memory and returns a new string, putting U+FFFD in place of anything invalid. Never traps on the contents.
Stack
[i32 i32] → [stringref]
Address in memory x, then how many code units to read.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Reads WTF-8 bytes from memory and returns a new string. Traps if they are not valid WTF-8.
WTF-8: UTF-8 extended to allow isolated surrogates, the lone halves of surrogate pairs that a JavaScript string can hold and UTF-8 cannot encode.
Stack
[i32 i32] → [stringref]
Address in memory x, then how many code units to read.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Writes the string to memory as UTF-8, putting U+FFFD in place of any isolated surrogate. Never traps on the contents.
Nothing bounds the write but the memory itself, so measure first.
Stack
[stringref i32] → [i32]
The string, then the destination address in memory x. Pushes how many code units were written.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Writes the string to memory as WTF-8, which holds anything a string can contain, so it never traps on the contents.
WTF-8: UTF-8 extended to allow isolated surrogates, the lone halves of surrogate pairs that a JavaScript string can hold and UTF-8 cannot encode.
Stack
[stringref i32] → [i32]
The string, then the destination address in memory x. Pushes how many code units were written.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Writes part of the view to memory as UTF-8, up to a byte count. Traps on an isolated surrogate.
WTF-8: UTF-8 extended to allow isolated surrogates, the lone halves of surrogate pairs that a JavaScript string can hold and UTF-8 cannot encode.
Stack
[stringview_wtf8 i32 i32 i32] → [i32 i32]
The view, the destination address in memory x, the byte offset to start at, then how many bytes to write at most. Pushes the offset it reached, then how many bytes it wrote.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Writes part of the view to memory as UTF-8, up to a byte count, putting U+FFFD in place of any isolated surrogate.
WTF-8: UTF-8 extended to allow isolated surrogates, the lone halves of surrogate pairs that a JavaScript string can hold and UTF-8 cannot encode.
Stack
[stringview_wtf8 i32 i32 i32] → [i32 i32]
The view, the destination address in memory x, the byte offset to start at, then how many bytes to write at most. Pushes the offset it reached, then how many bytes it wrote.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Writes part of the view to memory as WTF-8, up to a byte count.
WTF-8: UTF-8 extended to allow isolated surrogates, the lone halves of surrogate pairs that a JavaScript string can hold and UTF-8 cannot encode.
Stack
[stringview_wtf8 i32 i32 i32] → [i32 i32]
The view, the destination address in memory x, the byte offset to start at, then how many bytes to write at most. Pushes the offset it reached, then how many bytes it wrote.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Writes part of the view to memory as 16-bit code units, up to a given count.
WTF-16: UTF-16 extended to allow isolated surrogates, which is exactly what a JavaScript string is.
Stack
[stringview_wtf16 i32 i32 i32] → [i32]
The view, the destination address in memory x, the code-unit offset to start at, then how many code units to write at most. Pushes how many it wrote.
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Copy from a passive data segment to linear memory.
Bulk Memory Operations.
Stack
[i32 i32 i32] → []
Immediate operands
u32 y : dataidx
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Copy from one region of linear memory to another region.
Bulk Memory Operations.
Stack
[i32 i32 i32] → []
Immediate operands
u32 x : memidx
u32 y : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Fill a region of linear memory with a given byte value.
Bulk Memory Operations.
Stack
[i32 i32 i32] → []
Immediate operands
u32 x : memidx
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Adds two 128-bit integers, each held in a pair of i64 values. Overflow wraps.
WebAssembly has no 128-bit integer type, so without this an addition has to be built from an add and a separate carry calculation.
Stack
[i64 i64 i64 i64] → [i64 i64]
Each 128-bit value is two operands, low half first, so the four operands are the low and high halves of the first value then those of the second. The results are in the same order: low half, then high half.
Subtracts the second 128-bit integer from the first, each held in a pair of i64 values. Underflow wraps.
WebAssembly has no 128-bit integer type, so without this a subtraction has to be built from a subtract and a separate borrow calculation.
Stack
[i64 i64 i64 i64] → [i64 i64]
Each 128-bit value is two operands, low half first, so the four operands are the low and high halves of the first value then those of the second. The results are in the same order: low half, then high half.
Multiplies two signed 64-bit integers and keeps the whole 128-bit product, where i64.mul keeps only the low half.
i64.mul needs no signed and unsigned form because the low half of the product is the same either way. The high half is not, which is why these two exist.
Stack
[i64 i64] → [i64 i64]
The results are the low 64 bits of the product, then the high 64 bits.
Multiplies two unsigned 64-bit integers and keeps the whole 128-bit product, where i64.mul keeps only the low half.
i64.mul needs no signed and unsigned form because the low half of the product is the same either way. The high half is not, which is why these two exist.
Stack
[i64 i64] → [i64 i64]
The results are the low 64 bits of the product, then the high 64 bits.
Part of the half-precision proposal, which adds the 16-bit float type f16 and a f16x8 vector shape.
Loads two bytes as an f16 and promotes the result to f32.
Stack
[i32] → [f32]
Half precision: f16 is not a WebAssembly value type. The scalar operand and result are f32, rounded to half precision.
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Part of the half-precision proposal, which adds the 16-bit float type f16 and a f16x8 vector shape.
Demotes an f32 to f16 and stores it as two bytes.
Stack
[i32 f32] → []
Half precision: f16 is not a WebAssembly value type. The scalar operand and result are f32, rounded to half precision.
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Reads eight bytes and sign-extends each to 16 bits, giving an i16x8 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Reads eight bytes and zero-extends each to 16 bits, giving an i16x8 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Reads eight bytes as four 16-bit values and sign-extends each to 32 bits, giving an i32x4 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Reads eight bytes as four 16-bit values and zero-extends each to 32 bits, giving an i32x4 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Reads eight bytes as two 32-bit values and sign-extends each to 64 bits, giving an i64x2 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Reads eight bytes as two 32-bit values and zero-extends each to 64 bits, giving an i64x2 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Load a single element and splat to all lanes of a v128 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Load a single element and splat to all lanes of a v128 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Load a single element and splat to all lanes of a v128 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Load a single element and splat to all lanes of a v128 vector.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Builds a new vector one byte at a time, each byte picked from the two operands by an immediate index.
Stack
[v128 v128] → [v128]
Immediate operands
u8[16] l* : laneidx — one per result lane, each 0–31 selecting a byte of the two inputs
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Extracts one lane from a 128-bit vector read as 16 packed i8 numbers.
Stack
[v128] → [i32]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Extracts a lane from a 128-bit vector interpreted as 16 packed u8 numbers.
Stack
[v128] → [i32]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Replaces one lane of a 128-bit vector read as 16 packed i8 numbers, leaving the others unchanged.
Stack
[v128 i32] → [v128]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Extracts a lane from a 128-bit vector interpreted as 8 packed i16 numbers.
Stack
[v128] → [i32]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Extracts a lane from a 128-bit vector interpreted as 8 packed u16 numbers.
Stack
[v128] → [i32]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Replaces a lane from a 128-bit vector interpreted as 8 packed i16 numbers.
Stack
[v128 i32] → [v128]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Extracts a lane from a 128-bit vector interpreted as 4 packed i32 numbers.
Stack
[v128] → [i32]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Replaces a lane from a 128-bit vector interpreted as 4 packed i32 numbers.
Stack
[v128 i32] → [v128]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Extracts a lane from a 128-bit vector interpreted as 2 packed i64 numbers.
Stack
[v128] → [i64]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Replaces a lane from a 128-bit vector interpreted as 2 packed i64 numbers.
Stack
[v128 i64] → [v128]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Extracts one lane from a 128-bit vector read as 4 packed f32 numbers.
Stack
[v128] → [f32]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Replaces one lane of a 128-bit vector read as 4 packed f32 numbers, leaving the others unchanged.
Stack
[v128 f32] → [v128]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Extracts one lane from a 128-bit vector read as 2 packed f64 numbers.
Stack
[v128] → [f64]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Replaces one lane of a 128-bit vector read as 2 packed f64 numbers, leaving the others unchanged.
Stack
[v128 f64] → [v128]
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Loads 8 bits from memory into lane l of the vector operand. Every other lane is copied through unchanged.
Stack
[i32 v128] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
u8 l : laneidx
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Loads 16 bits from memory into lane l of the vector operand. Every other lane is copied through unchanged.
Stack
[i32 v128] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
u8 l : laneidx
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Loads 32 bits from memory into lane l of the vector operand. Every other lane is copied through unchanged.
Stack
[i32 v128] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
u8 l : laneidx
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Loads 64 bits from memory into lane l of the vector operand. Every other lane is copied through unchanged.
Stack
[i32 v128] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
u8 l : laneidx
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Stores the 8 bits in lane l of the vector operand to memory.
Stack
[i32 v128] → []
Immediate operands
m : memarg — u32 align, then u64 offset
u8 l : laneidx
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Stores the 16 bits in lane l of the vector operand to memory.
Stack
[i32 v128] → []
Immediate operands
m : memarg — u32 align, then u64 offset
u8 l : laneidx
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Stores the 32 bits in lane l of the vector operand to memory.
Stack
[i32 v128] → []
Immediate operands
m : memarg — u32 align, then u64 offset
u8 l : laneidx
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Stores the 64 bits in lane l of the vector operand to memory.
Stack
[i32 v128] → []
Immediate operands
m : memarg — u32 align, then u64 offset
u8 l : laneidx
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Load a 32-bit element into the low bits of the vector and sets all other bits to zero.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Load a 64-bit element into the low bits of the vector and sets all other bits to zero.
Stack
[i32] → [v128]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Conversion of the two double-precision floating point lanes to two lower single-precision lanes of the result. The two higher lanes of the result are initialized to zero. If the conversion result is not representable as a single-precision floating point number, it is rounded to the nearest-even representable number.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
An encoding used while relaxed SIMD was being prototyped. Relaxed SIMD was standardised in the 0xFD 256 and above range, and this slot is unassigned again.
Stack
[v128 v128] → [v128]
Relaxed: an engine may pick among several permitted results for the same input. The deterministic profile fixes one choice.
As i8x16.swizzle, except that an index outside 0 to 15 gives an implementation-defined result rather than 0.
Stack
[v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Relaxed i32x4.trunc_f32x4_s (relaxed version of i32x4.trunc_sat_f32x4_s).
This instruction has the same behavior as the non-relaxed instruction for lanes that are in the range of an i32 (signed or unsigned depending on the instruction). The result of lanes which contain NaN is implementation defined, either 0 or INT32_MAX for signed and UINT32_MAX for unsigned. The result of lanes which are out of bounds of INT32 or UINT32 is implementation defined, it can be either the saturated result or INT32_MAX for signed and UINT32_MAX for unsigned.
Stack
[v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Relaxed i32x4.trunc_f32x4_u (relaxed version of i32x4.trunc_sat_f32x4_u).
This instruction has the same behavior as the non-relaxed instruction for lanes that are in the range of an i32 (signed or unsigned depending on the instruction). The result of lanes which contain NaN is implementation defined, either 0 or INT32_MAX for signed and UINT32_MAX for unsigned. The result of lanes which are out of bounds of INT32 or UINT32 is implementation defined, it can be either the saturated result or INT32_MAX for signed and UINT32_MAX for unsigned.
Stack
[v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Relaxed i32x4.trunc_f64x2_s_zero (relaxed version of i32x4.trunc_sat_f64x2_s_zero).
This instruction has the same behavior as the non-relaxed instruction for lanes that are in the range of an i32 (signed or unsigned depending on the instruction). The result of lanes which contain NaN is implementation defined, either 0 or INT32_MAX for signed and UINT32_MAX for unsigned. The result of lanes which are out of bounds of INT32 or UINT32 is implementation defined, it can be either the saturated result or INT32_MAX for signed and UINT32_MAX for unsigned.
Stack
[v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Relaxed i32x4.trunc_f64x2_u_zero (relaxed version of i32x4.trunc_sat_f64x2_u_zero).
This instruction has the same behavior as the non-relaxed instruction for lanes that are in the range of an i32 (signed or unsigned depending on the instruction). The result of lanes which contain NaN is implementation defined, either 0 or INT32_MAX for signed and UINT32_MAX for unsigned. The result of lanes which are out of bounds of INT32 or UINT32 is implementation defined, it can be either the saturated result or INT32_MAX for signed and UINT32_MAX for unsigned.
Stack
[v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
the intermediate a * b is be rounded first, and the final result rounded again (for a total of 2 roundings), or
the entire expression evaluated with higher precision and then only rounded once (if supported by hardware).
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
the intermediate a * b is be rounded first, and the final result rounded again (for a total of 2 roundings), or
the entire expression evaluated with higher precision and then only rounded once (if supported by hardware).
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
the intermediate a * b is be rounded first, and the final result rounded again (for a total of 2 roundings), or
the entire expression evaluated with higher precision and then only rounded once (if supported by hardware).
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
the intermediate a * b is be rounded first, and the final result rounded again (for a total of 2 roundings), or
the entire expression evaluated with higher precision and then only rounded once (if supported by hardware).
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Select lanes from a or b based on masks in m. If each lane-sized mask in m has all bits set or all bits unset, these instructions behave the same as v128.bitselect. Otherwise, the result is implementation defined.
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Select lanes from a or b based on masks in m. If each lane-sized mask in m has all bits set or all bits unset, these instructions behave the same as v128.bitselect. Otherwise, the result is implementation defined.
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Select lanes from a or b based on masks in m. If each lane-sized mask in m has all bits set or all bits unset, these instructions behave the same as v128.bitselect. Otherwise, the result is implementation defined.
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Select lanes from a or b based on masks in m. If each lane-sized mask in m has all bits set or all bits unset, these instructions behave the same as v128.bitselect. Otherwise, the result is implementation defined.
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Return the lane-wise minimum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined.
Stack
[v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Return the lane-wise maximum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined.
Stack
[v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Return the lane-wise minimum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined.
Stack
[v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Return the lane-wise maximum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined.
Stack
[v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Returns the multiplication of 2 fixed-point numbers in Q15 format. If both inputs are INT16_MIN, the result overflows, and the return value is implementation defined (either INT16_MIN or INT16_MAX).
Stack
[v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Reads the first operand as 16 signed 8-bit integers and the second as 16 unsigned 7-bit integers, multiplies them lane by lane, then adds each adjacent pair of products to give 8 i16 lanes.
If a lane of the second operand has its high bit set, that lane’s result is implementation-defined.
Stack
[v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Reads the first operand as 16 signed 8-bit integers and the second as 16 unsigned 7-bit integers and multiplies them lane by lane, as i16x8.relaxed_dot_i8x16_i7x16_s does. Adds each group of four adjacent products to give 4 i32 lanes, then adds those to the third operand.
If a lane of the second operand has its high bit set, that lane’s result is implementation-defined.
Stack
[v128 v128 v128] → [v128]
Status
Relaxed SIMDStandardised in WebAssembly 3.0 (2025)Standardised. Results may differ between engines by design — that is the point of the relaxation.Engine support
Part of the half-precision proposal, which adds the 16-bit float type f16 and a f16x8 vector shape.
Stack
[v128] → [f32]
Half precision: f16 is not a WebAssembly value type. The scalar operand and result are f32, rounded to half precision.
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Part of the half-precision proposal, which adds the 16-bit float type f16 and a f16x8 vector shape.
Stack
[v128 f32] → [v128]
Half precision: f16 is not a WebAssembly value type. The scalar operand and result are f32, rounded to half precision.
Immediate operands
u8 l : laneidx
Lane index: counts from 0. A value at or past the number of lanes is rejected when the module is validated, so it can never be out of range at run time.
Wakes agents waiting at an address and returns how many were woken.
Stack
[i32 i32] → [i32]
The operands are the address and the maximum number of agents to wake. Fewer may be woken, and none if none were waiting. Notifying an unshared memory is allowed and wakes nothing, since a wait on one traps.
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Waits for a notification at an address, if the 32-bit value there is still the expected one. Pushes why the wait ended:
0: woken by memory.atomic.notify.
1: the value at the address was not the expected one, so it did not wait.
2: the timeout expired.
Stack
[i32 i32 i64] → [i32]
The operands are the address, the expected value, then a timeout in nanoseconds; a negative timeout never expires. Traps on an unshared memory. A host can forbid an agent from blocking: in a browser only a worker can wait, not the main thread.
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Waits for a notification at an address, if the 64-bit value there is still the expected one. Pushes why the wait ended:
0: woken by memory.atomic.notify.
1: the value at the address was not the expected one, so it did not wait.
2: the timeout expired.
Stack
[i32 i64 i64] → [i32]
The operands are the address, the expected value, then a timeout in nanoseconds; a negative timeout never expires. Traps on an unshared memory. A host can forbid an agent from blocking: in a browser only a worker can wait, not the main thread.
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Mostly a change to what the atomic instructions mean rather than a set of new ones: it gives them an ordering immediate. Adds `pause`. Encoding not final.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, load, i32, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE17:u32i64.atomic.load m
read from memory
Description
Atomically load 8 bytes as i64.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, load, i64, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE18:u32i32.atomic.load8_u m
read 1 byte from memory, zero-extended
Description
Atomically load 1 byte and zero-extend i8 to i32.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, load, i32, unsigned, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE19:u32i32.atomic.load16_u m
read 2 bytes from memory, zero-extended
Description
Atomically load 2 bytes and zero-extend i16 to i32.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, load, i32, unsigned, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE20:u32i64.atomic.load8_u m
read 1 byte from memory, zero-extended
Description
Atomically load 1 byte and zero-extend i8 to i64.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, load, i64, unsigned, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE21:u32i64.atomic.load16_u m
read 2 bytes from memory, zero-extended
Description
Atomically load 2 bytes and zero-extend i16 to i64.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, load, i64, unsigned, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE22:u32i64.atomic.load32_u m
read 4 bytes from memory, zero-extended
Description
Atomically load 4 bytes and zero-extend i32 to i64.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, load, i64, unsigned, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE23:u32i32.atomic.store m
write to memory
Description
(no conversion) atomically store 4 bytes.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32 i32] → []
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, store, i32, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE24:u32i64.atomic.store m
write to memory
Description
(no conversion) atomically store 8 bytes.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32 i64] → []
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, store, i64, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE25:u32i32.atomic.store8 m
write the low 1 byte to memory
Description
Wrap i32 to i8 and atomically store 1 byte.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32 i32] → []
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, store, i32, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE26:u32i32.atomic.store16 m
write the low 2 bytes to memory
Description
Wrap i32 to i16 and atomically store 2 bytes.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32 i32] → []
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, store, i32, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE27:u32i64.atomic.store8 m
write the low 1 byte to memory
Description
Wrap i64 to i8 and atomically store 1 byte.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32 i64] → []
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, store, i64, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE28:u32i64.atomic.store16 m
write the low 2 bytes to memory
Description
Wrap i64 to i16 and atomically store 2 bytes.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32 i64] → []
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, store, i64, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE29:u32i64.atomic.store32 m
write the low 4 bytes to memory
Description
Wrap i64 to i32 and atomically store 4 bytes.
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
Stack
[i32 i64] → []
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Widely implemented, but not yet folded into the specification.Engine support
Properties
Atomic, Atomic load and store, store, i64, 2-byte opcode, takes immediates, proposal, Threads and atomics.
0xFE30:u32i32.atomic.rmw.add m
add
Description
32-bit sign-agnostic addition.
Read: 4 bytes, Write: 4 bytes
Returns: as i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
32-bit exchange: writes the operand to the address and returns the value that was there.
Read: 4 bytes, Write: 4 bytes
Returns: as i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
64-bit exchange: writes the operand to the address and returns the value that was there.
Read: 8 bytes, Write: 8 bytes
Returns: as i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
8-bit exchange: writes the operand to the address and returns the value that was there.
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
16-bit exchange: writes the operand to the address and returns the value that was there.
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
8-bit exchange: writes the operand to the address and returns the value that was there.
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
16-bit exchange: writes the operand to the address and returns the value that was there.
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
32-bit exchange: writes the operand to the address and returns the value that was there.
Read: 4 bytes, Write: 4 bytes
Returns: zero-extended i32 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Stack
[i32 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Compare expected with loaded: 32-bit compare equal.
Conditionally Store replacement: store 4 bytes.
Return loaded: as i32.
Stack
[i32 i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Compare expected with loaded: 64-bit compare equal.
Conditionally Store replacement: 8 bytes.
Return loaded: as i64.
Stack
[i32 i64 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Compare expected with loaded: `expected` wrapped from i32 to i8, 8-bit compare equal.
Conditionally Store replacement: wrapped from i32 to i8, store 1 byte.
Return loaded: zero-extended from i8 to i32.
Stack
[i32 i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Compare expected with loaded: `expected` wrapped from i32 to i16, 16-bit compare equal.
Conditionally Store replacement: wrapped from i32 to i16, store 2 bytes.
Return loaded: zero-extended from i8 to i32.
Stack
[i32 i32 i32] → [i32]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Compare expected with loaded: `expected` wrapped from i64 to i8, 8-bit compare equal.
Conditionally Store replacement: wrapped from i64 to i8, store 1 byte.
Return loaded: zero-extended from i8 to i64.
Stack
[i32 i64 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Compare expected with loaded: `expected` wrapped from i64 to i16, 16-bit compare equal.
Conditionally Store replacement: wrapped from i64 to i16, store 2 bytes.
Return loaded: zero-extended from i16 to i64.
Stack
[i32 i64 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Compare expected with loaded: `expected` wrapped from i64 to i32, 32-bit compare equal.
Conditionally Store replacement: wrapped from i64 to i32, store 4 bytes.
Return loaded: zero-extended from i32 to i64.
Stack
[i32 i64 i64] → [i64]
Immediate operands
m : memarg — u32 align, then u64 offset
Alignment
align is the base-2 logarithm of the assumed alignment in bytes: 0 for 1 byte, 1 for 2, 2 for 4, 3 for 8, 4 for 16.
A value larger than the width of the access is rejected when the module is validated. A smaller one is allowed, and only tells the engine not to assume alignment.
Bit 6 (0x40) is not part of the number. When it is set, a u32 memory index follows align, before the offset, and the alignment is what is left after subtracting 64. When it is clear, the instruction uses memory 0.
Addresses: an i32 for a 32-bit memory, an i64 for a 64-bit memory (memory64). The signatures here show the 32-bit case, which is what almost every module uses.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically adds to a shared global, returning the value it held before.
Stack
[t] → [t]
t is the type of global x. Pushes the value the global held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : globalidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically subtracts from a shared global, returning the value it held before.
Stack
[t] → [t]
t is the type of global x. Pushes the value the global held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : globalidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-ands a shared global, returning the value it held before.
Stack
[t] → [t]
t is the type of global x. Pushes the value the global held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : globalidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-ors a shared global, returning the value it held before.
Stack
[t] → [t]
t is the type of global x. Pushes the value the global held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : globalidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-xors a shared global, returning the value it held before.
Stack
[t] → [t]
t is the type of global x. Pushes the value the global held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : globalidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically replaces a shared global, returning the value it held before.
Stack
[t] → [t]
t is the type of global x. Pushes the value the global held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : globalidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically replaces a shared global, if it holds an expected value, returning the value it held before.
Stack
[tt] → [t]
t is the type of global x. The expected value, then the replacement; pushes the value the global held before.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : globalidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically replaces a table element, returning the reference it held before.
Stack
[i32 t] → [t]
t is the element type of table x. Pushes the element held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : tableidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically replaces a table element, if it matches an expected reference, returning the reference it held before.
Stack
[i32 tt] → [t]
t is the element type of table x. Index, expected value, then the replacement; pushes the element held before.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : tableidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically adds to a struct field, returning the value it held before.
Stack
[(ref null x) t] → [t]
t is the type of field y of struct type x. Pushes the value the field held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
u32 y : fieldidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically subtracts from a struct field, returning the value it held before.
Stack
[(ref null x) t] → [t]
t is the type of field y of struct type x. Pushes the value the field held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
u32 y : fieldidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-ands a struct field, returning the value it held before.
Stack
[(ref null x) t] → [t]
t is the type of field y of struct type x. Pushes the value the field held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
u32 y : fieldidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-ors a struct field, returning the value it held before.
Stack
[(ref null x) t] → [t]
t is the type of field y of struct type x. Pushes the value the field held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
u32 y : fieldidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-xors a struct field, returning the value it held before.
Stack
[(ref null x) t] → [t]
t is the type of field y of struct type x. Pushes the value the field held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
u32 y : fieldidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically replaces a struct field, returning the value it held before.
Stack
[(ref null x) t] → [t]
t is the type of field y of struct type x. Pushes the value the field held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
u32 y : fieldidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically replaces a struct field, if it holds an expected value, returning the value it held before.
Stack
[(ref null x) tt] → [t]
t is the type of field y of struct type x. The expected value, then the replacement; pushes the value the field held before.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
u32 y : fieldidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically adds to an array element, returning the value it held before.
Stack
[(ref null x) i32 t] → [t]
t is the element type of array type x. Pushes the element held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically subtracts from an array element, returning the value it held before.
Stack
[(ref null x) i32 t] → [t]
t is the element type of array type x. Pushes the element held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-ands an array element, returning the value it held before.
Stack
[(ref null x) i32 t] → [t]
t is the element type of array type x. Pushes the element held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-ors an array element, returning the value it held before.
Stack
[(ref null x) i32 t] → [t]
t is the element type of array type x. Pushes the element held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically bitwise-xors an array element, returning the value it held before.
Stack
[(ref null x) i32 t] → [t]
t is the element type of array type x. Pushes the element held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically replaces an array element, returning the value it held before.
Stack
[(ref null x) i32 t] → [t]
t is the element type of array type x. Pushes the element held before the write.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.
Atomically replaces an array element, if it holds an expected value, returning the value it held before.
Stack
[(ref null x) i32 tt] → [t]
t is the element type of array type x. Index, expected value, then the replacement; pushes the element held before.
Immediate operands
u8 ord : ordering — 0x00 seqcst, 0x11 acqrel
u32 x : typeidx
Ordering byte: a read-modify-write packs the read ordering into the low four bits and the write ordering into the high four, and the two must match, so no other byte is valid.
Implemented behind a flag in V8, but still an early proposal. Extends atomics from linear memory to globals, tables and GC objects. Encoding not final.